1. Field of the Invention
The present invention relates to a functional block and a semiconductor integrated circuit into which a plurality of functional blocks are incorporated in combination and, more particularly, an LSI design technology using functional blocks whose delay analysis can be facilitated.
2. Description of the Related Art
In the prior art, normally system designers have architected a desired system by arranging a plurality LSI chips on a printed wiring board and then providing wiring between them. The LSI manufacturers have fabricated LSI chips for respective functions such as CPU, memory, peripheral circuit, etc.
In recent years, with the progress of miniaturization and higher density of LSI, several millions of transistors have been incorporated on one chip. Therefore, a plurality of functions have been able to be mounted on one chip. That is, the change from silicon-on-system to system-on-silicon has been brought about. In order to answer to such change to the system-on-silicon, the LSI manufacturers have kept a large number of functional blocks which are constructed in each functional unit such as CPU, peripheral circuit, etc. and also enhanced the functional blocks as a library. Such library has been assembled by preparing circuit information and layout information concerning the kept functional blocks as the database. The LSI manufacturers have implemented the LSI by using various functional blocks which are prepared in the library in combination. By employing the above library, the LSI manufacturers can take quick responses to new LSI development requests issued from the system designers respectively.
A functional block in the prior art will be explained with reference to FIG. 1 hereinafter. FIG. 1 shows an example of a configuration of the functional block in the prior art. A functional block 1 comprises a function portion 2, a plurality of input terminals 3-1, 3-2, 3-3, . . . , 3-m (where m is a natural number) connected to the function portion 2, a plurality of output terminals 4-1, 4-2, 4-3, . . . , 4-n (where n is a natural number), a clock input terminal 5 for receiving a clock signal CLK, and a reset input terminal 6 for receiving a reset signal RST. The function portion 2 can perform predetermined operations of a plurality of input signals IN1, IN2, IN3, . . . , INm supplied from the input terminals 3-1, 3-2, . . . , 3-m, and then output results of the operations from the output terminals 4-1, 4-2, 4-3, . . . , 4-n as output signals OUT1, OUT2, OUT3, . . . , OUTn. The clock signal CLK and the reset signal RST are supplied to the function portion 2. The clock signal CLK is a signal used as reference in carrying out a synchronous operation. The functional block 1 can perform the synchronous operation on a basis of the clock signal CLK. Regardless of its present state, the functional block 1 can be brought into its reset state by the reset signal RST.
The function portion 2 has a plurality of logic portions 7-1, 7-2, 7-3, . . . , 7-k (where k is a natural number). The logic portions 7-1, . . . , 7-k can receive at least one of plural input signals IN1, IN2, . . . , INm and generate the output signals OUT1, OUT2, . . . , OUTn respectively. In some cases, the function portion 2 has synchronizing circuits such as flip-flops, though not illustrated.
Further, the flip-flops serving as the synchronizing circuits are arranged at need on the input side and the output side of the function portion 2. For example, in FIG. 1, a flip-flop 8 is arranged on the input side of the function portion 2 while a flip-flop 9 is arranged on the output side of the function portion 2. In other words, the flip-flop 8 is connected between an input terminal 3-1 and a logic portion 7-1 while the flip-flop 9 is connected between a logic portion 7-2 and an output terminal 4-2. A clock signal CLK input from the clock input terminal 5 is supplied to both clock terminals CK of the flip-flop 8 and the flip-flop 9 via a buffer 10. The flip-flop 8 can receive the input signal IN1 and then output the input signal IN1 to the logic portion 7-1 in synchronous with the clock signal CLK. The flip-flop 9 can receive the output signal of the logic portion 7-2 and then output it to the output terminal 4-2 as the output signal OUT2 in synchronous with the clock signal CLK. In addition, the reset signal RST is input into the reset terminals R of both flip-flops via a buffer 11. Both the flip-flops 8, 9 can be brought into their reset states by the reset signal RST irrespective of their present states.
In this way, in the functional block in the prior art, the function portion 2 can generate the output signals OUT1, OUT2, OUT3, . . . , OUTn in response to the input signals IN1, IN2, IN3, . . . , INm being input from the input terminals 3-1, 3-2, 3-3, . . . , 3-m, and then output such output signals OUT1, OUT2, OUT3, . . . , OUTn to the output terminals 4-1, 4-2, 4-3, . . . , 4-n via buffers 12-1, 12-2, 12-3, . . . , 12-n respectively.
In order to manufacture the products in accordance with specifications, it is common for the LSI manufacturer to execute the function, timing and other design verifications by virtue of simulation with using a computer system before manufacture and then start actual manufacturing steps after the verifications has been completed. The verifications can be conducted based on a functional model which can be architected by combining the functional blocks together. Timing specifications for respective functional blocks have been very important in the verifications. However, in recent years, circuit configurations of respective functional blocks have become more complicated according to increases in the scale and the operational speed of the LSI, so that it has not been easy to precisely define the delay time of the output signals for the input signals of the functional blocks. As a result, the verifications based on the above simulation has become difficult.
For example, an AND-OR circuit composed of a two-input AND gate and a two-input OR gate will be explained. In this AND-OR circuit, an output of the AND gate and one input A of the OR gate are connected. Only if the output of the AND gate is 0, an output change of the OR gate depends on other input B change of the OR gate. The output of the AND gate is 0 only when a combination of the inputs of the AND gate is (0,0), (0,1), (1,0). In this OR gate, there are certain differences in delay time of the output for the input B according to the inputs of the AND gate.
Like this, the delay time of one output for one input depends on the state of others. Nevertheless, shown in FIG. 1, the functional block in which a number of such logic circuits has a large number of input signals. Therefore, it is very difficult in practice to define clearly the delay time. One of causes is that a plurality of signal transmission lines are present from one input to one output. The second cause is that it cannot be decided from the state of the inputs which line has been taken. The third cause is that it is decided from the output signal change which input signal has changed.
Meanwhile, the flip-flop 8 is provided between the input terminal 3-1 and the logic portion 7-1. The input signal IN1 is fetched into the flip-flop 8 once. The flip-flop 8 outputs the input signal IN1 to the logic portion 7-1 in synchronous with the clock signal CLK. However, it is still difficult to define the delay time caused from an output Q of the flip-flop 8 to the output terminal 4-1. Then, the flip-flop 9 is connected on the output side of the logic portion 7-2. Hence, the logic portion 7-2 can output the output signal OUT2 to the output terminal 4-2 in synchronous with the clock signal CLK. However, there exists no synchronizing circuit on the input side. Thus, it is difficult to define the delay time caused from the input terminal 3-2 to an input of the logic portion 7-2.
Furthermore, in the logic portions 7-1, . . . , 7-k in FIG. 1, it is also possible to say the same thing as above. FIG. 2 shows an example of one configuration of the logic portions 7-1, . . . , 7-k shown in FIG. 1. The logic portion 13 in FIG. 2 has a plurality of random logics 14-1, 14-2, 14-3, . . . , 14-l (where l is a natural number), and a selector 15 for selecting one of the outputs from the plurality of random logics 14-1, 14-2, 14-3, . . . , 14-l based on a select signal SELECT and outputting it. Inputs of the logic portion 13 are connected to a flip-flop 16, a flip-flop 17, and a flip-flop 18 provided on the outside of the functional block. Then, an output of the logic portion 13 is connected to a flip-flop 19 provided in the functional block. A plurality of signal transmission lines are present from the flip-flop 16, the flip-flop 17, and the flip-flop 18 to the flip-flop 19 in the logic portion 13. The delay time which is required for the signal to come up to the flip-flop 19 is different based on which route such signal has taken. As a consequence, it is not easy to define the delay time.
FIG. 3 shows another example of one configuration of the logic portions 7-1, 7-2, . . . , 7-k shown in FIG. 1. A logic portion 20 in FIG. 3 has a plurality of random logics 21-1, 21-2, . . . , 21-l, and a selector 22 for selecting one of the outputs from the plurality of random logics 21-1, 21-2, . . . , 21-l based on the select signal SELECT and outputting it. Inputs of the logic portion 20 are connected to a flip-flop 23, and a flip-flop 24 connected in the inside of the functional block. Then, an output of the logic portion 20 is connected to a flip-flop 25 on the outside of the functional block. A plurality of signal transmission lines exist from the flip-flop 23, and the flip-flop 24 to the flip-flop 25 in the logic portion 20. Normally, in synchronous design, the delay time in the output of the functional block is defined by using the clock signal as a reference. However, since there exist a plurality of routes in the above logic portion 20, actually the delay times are different on respective routes. Hence, definition of the precise delay time is not easy. Also, even if the delay times on respective routes can be defined precisely, it is still difficult to define precisely the delay time in the logic portion 20. This is because, in case the select signal SELECT is controlled according to an internal state of the logic portion 20, it cannot be decided from the outside of the logic portion 20 which route has been taken by the output signal.
An ASIC such as gate array, standard array, etc. is architected by installing a combination of a plurality of functional blocks. For example, the case will be discussed where an output of one functional block (called a "functional block A" herein) is input into the other functional block (called a "functional block B" herein). The delay time caused in the functional block A becomes different according to an input state of the functional block A. Therefore, there is such a possibility that an output of the functional block A is provided against a timing constraint on an input of the functional block B to thus cause a failure of the functional block B. In addition, with the miniaturization and the higher operational speed of the LSI, the signal delay which is caused by wiring connecting the output of the functional block A to the input of the functional block B has been increased to such an extent that it cannot be ignored. Therefore, there is a possibility that, even if an operation of the functional block as a single body can be assured, an operation of the integrated circuit in which a plurality of functional blocks are incorporated in combination cannot be ensured yet. Especially, in the event that the synchronizing circuits such as flip-flops, etc. are employed, their operations cannot be ensured unless a specified setup time or hold time can be taken.
In view of the above respects, it is indispensable before start of the production to perform the behavior confirmation by using simulation. However, in the existing circumstance that the precise definition of the delay time has not been made easy, as stated above, such simulation has become very difficult.
Moreover, even if the definition of the delay time has been given and also the failure in operation has been confirmed by virtue of simulation, correction of the functional blocks cannot be performed in practice. This is because such correction of the functional blocks takes the same cost and time as the case where the functional blocks are newly developed and such correction is contrary to an approach to achieve the quickness of the development with use of the functional blocks which have been registered in the library. Therefore, in the existing circumstances, only correction can be applied to such a degree that the wiring delay is reduced by, for example, inserting timing adjusting circuits (e.g., buffers) in the wiring to connect the functional blocks, or the like. For example, FIG. 4 shows an example of a configuration in which the above timing adjusting circuits are inserted between the functional blocks. The functional block 26 and the functional block 27 are connected to each other via lines 28-1, 28-2, 28-3, . . . , 28-j (where j is a natural number). Then, a timing adjusting circuit 29 and a timing adjusting circuit 30 are inserted in the line 28-2 and the line 28-j respectively. The functional block 26 and the functional block 27 have a function portion 33 and a function portion 34, in which a plurality of logic portions 31 and a plurality of flip-flops 32 are arranged respectively. The clock signal CLK is supplied to respective clock input terminals via a common clock base line 35.